Newsarchive

News Archive

2020

Dec 9, 2020: Our work on Closing the RISC-V Compliance Gap via Fuzzing is presented at the RISC-V Summit 2020.
Nov 17, 2020: Our work on Clustering-guided SMT(LRA) learning is presented at the International Conference on integrated Formal Methods (iFM 2020).
Nov 9, 2020: Our work on ASNet: Introducing approximate hardware to high-level synthesis of neural networks is presented at the International Symposium on Multiple-Valued Logic (ISMVL 2020).
Oct 27, 2020: Daniel Große speaks in the tutorial “Cross-Level Compliance Testing and Verification for RISC-V” at the Design and Verification Conference and Exhibition Europe (DVCon 2020).
Oct 22, 2020: Our book Enhanced Virtual Prototyping: Featuring RISC-V Case Studies has been published by Springer.
Oct 20-21, 2020: Our work on RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms is presented at the International Symposium on Automated Technology for Verification and Analysis (ATVA 2020).
Oct 20, 2020: Daniel Große has been appointed as Program Committee Member of the Design Automation Conference (DAC) 2021.
Oct 20, 2020: Our work on Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime is presented at the International Conference on Computer Design (ICCD 2020).
Oct 15, 2020: Daniel Große has been appointed as Program Committee Member of the GMM/ITG/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 2021.
Sep 17, 2020: We received the Best Paper Award for our paper Efficient cross-level testing for processor verification: A RISC-V case-study at the Forum on specification & Design Languages (FDL 2020).
Sep 17, 2020: Daniel Große has been appointed as Program Chair of the Forum on specification & Design Languages (FDL) 2021.
Sep 9-10, 2020: Our works on (i) Early Verification of ISA Extension Specifications using Deep Reinforcement Learning and (ii) Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes are presented at the ACM Great Lakes Symposium on VLSI (GLSVLSI 2020).
Jul 20-24, 2020: Our works on (i) Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side, (ii) Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes and (iii) Verification for Field-coupled Nanocomputing Circuits are presented at the Design Automation Conference (DAC 2020).